Verilog task that uses a for loop to describe an iterative combinational circuit that compares two 8-bit operands A and B for equality E, and greater than G. Instantiate the task in a testbench and

simulate it for operands such that every bit of A and B take on value 1 and 0 sometime during the test and the outputs E and G take on all four possible combinations.

module compar(G,E,A,B);

  input [7:0]A,B;

  output reg E;

  output reg G;

  always@(A,B)

    operation(G,E,A,B);

task operation;

  output reg G;

  output reg E;

  input [7:0]A,B;

  reg [7:0]x;

  reg sum,prod;

  integer i,j;

  begin

    for(i=0;i<8;i=i+1)

    begin

    x[i]=A[i]~^B[i];

  end

  E=&x;

    sum=0;

    for(i=0;i<8;i=i+1)

    begin

    j=i+1;

    prod=A[i]&(~B[i]);

    while(j<8)

    begin

    prod=x[j]&prod;

    j=j+1;

  end

  sum=sum|prod;

end

   G=sum;

        end

endtask

endmodule

TESTBENCH

module compar_tb;

reg [7:0]A,B;

  wire E,G;

compar C1(G,E,A,B);

initial

begin

  A=00001111;

  B=00000000;

  #100 A=00000011;

  B=00100000;

   #100 A=00000011;

  B=00000111;

   #100 A=00000011;

  B=0000010;

   #100 A=11111111;

  B=11111111;

  #200 $finish;

end

endmodule