Decoder and Encoder using case statements in Verilog
module decod_bm(ain, y);
input [2:0] ain;
output reg [7:0] y;
always@(ain)
begin
case(ain)
3'b000:y=8'b00000001;
3'b001:y=8'b00000010;
3'b010:y=8'b00000100;
3'b011:y=8'b00001000;
3'b100:y=8'b00010000;
3'b101:y=8'b00100000;
3'b110:y=8'b01000000;
3'b111:y=8'b10000000;
default:y=4'bxxxx;
endcase
end
endmodule
TESTBENCH:
module decod_tb();
reg [2:0]IN;
wire [7:0] OUT;
decod_bm DCR(IN, OUT);
initial
begin
IN=3'b000;
#50; IN=3'b001;
#50; IN=3'b010;
#50; IN=3'b011;
#50; IN=3'b100;
#50; IN=3'b101;
#50; IN=3'b110;
#250 $finish;
End
endmodule
ENCODER
module encod_83(aout,yin);
input [7:0] yin;
output reg [2:0] aout;
always@(yin)
begin
case(yin)
8'b00000001:aout=3'b000;
8'b00000010:aout=3'b001;
8'b00000100:aout=3'b010;
8'b00001000:aout=3'b011;
8'b00010000:aout=3'b100;
8'b00100000:aout=3'b101;
8'b01000000:aout=3'b110;
8'b10000000:aout=3'b111;
default:aout=2'bxx;
endcase
end
endmodule
TESTBENCH:
module encod_tb();
reg [7:0] IN;
wire [2:0] OUT;
encod_83 ENCR(OUT,IN);
initial
begin
IN=8'b00000001;
#50; IN=8'b00000010;
#50; IN=8'b00000100;
#50; IN=8'b00001000;
#50; IN=8'b00010000;
#50; IN=8'b00100000;
#50; IN=8'b01000000;
#250 $finish;
end
endmodule
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