Multiplexer and De-multiplexer using nested if-else construct in Verilog

MULTIPLEXER 4-to-1

module mux_41(a,b,c,d,sel,y);

  input a,b,c,d;

  input [1:0]sel;

  output reg y;

always @(sel,a,b,c,d)

begin

if(sel[1]==0)

if(sel[0]==0)

y=a;

else

y=b;

else

if(sel[0]==0)

y=c;

else

y=d;

end

endmodule

TESTBENCH

module mux_41_tb();

  reg A,B,C,D;

  reg [1:0]SEL;

  wire Y;

mux_41 M1(A,B,C,D,SEL,Y);

  initial

  begin

    A=1;    B=0;    C=1;    D=0;

   SEL[0]=0;   SEL[1]=0;

    #150;    SEL[0]=1;

    #150;     SEL[1]=1;     SEL[0]=0;

    #150;     SEL[0]=1;

    #250 $finish;

  end

endmodule

DEMULTIPLEXER

module demux_14(d,sel,y);

  output reg [3:0] y;

  input [1:0] sel;

  input d;

always @(sel or d)

begin

  y=4'b0000;

if(sel[1]==0)

if(sel[0]==0)

y[0]=d; 

else

y[1]=d;

else

if(sel[0]==0)

y[2]=d;

else

y[3]=d;

end

endmodule

TESTBENCH

module demux_14_tb();

  wire [3:0] Y;

  reg [1:0] SEL;

  reg D;

demux_14 DM(D,SEL,Y);

  initial

  begin

    D=1'b1;

   SEL=2'b10;

    #50;    SEL[0]=1;

    #50;     SEL[1]=0;     SEL[0]=0;

    #50;     SEL[0]=1;

    #250 $finish;

  end