Half-Subtractor and Full-Subtractor using dataflow modeling in Verilog

HALF SUBTRACTOR

module halfsub_df(a,b,diff,borr);

input a,b;

output diff,borr;

assign diff=a^b;

assign borr=~a&b;

endmodule

TESTBENCH:

module halfsub_tb();

  reg A,B;

  wire DIFF,BORR;

halfsub_df HA1(A,B,DIFF,BORR);

  initial

  begin

    A=0;    B=0;

    #50;    B=1;

    #50;     B=0;      A=1;

    #50;     B=1;

    #250 $finish;

  end

endmodule

FULL SUBTRACTOR

module fullsub_df(a,b,c,diff,borr);

input a,b,c;

output diff,borr;

assign diff=(a^b^c);

assign borr=((~a&b)|(~a&c)|(b&c));

endmodule

TESTBENCH:

module fullsub_tb();

  reg A,B,C;

  wire DIFF,BORR;

fullsub_df FS(A,B,C,DIFF,BORR);

  initial

  begin

    A=0;    B=0;    C=0;

    #50;    C=1;

    #50;    B=1;    C=0;

    #50;      C=1;

     #50;     A=1;     B=0;     C=0;

     #50;     C=1;

     #50;     C=0;     B=1;

     #50;     C=1;

    #250 $finish;

  end

endmodule