TWISTED RIGHT COUNTER

The RESET signal is a synchronous reset of the contents of the shift register to all 0’s. With reset inactive, on each positive edge on CLK, the twisted ring counter enters a new state. Due to the connection through the inverter, the twisted ring counter cycles through 2n different states on parallel_out where n is the number of bits in the shift register. Write a Verilog module description for the twisted ring counter shown using an always procedure to describe its activity.

module rtshift(clk,shift_out,reset,parallel_out);

input clk,reset;

output shift_out;

output [7:0]parallel_out;

reg [7:0]temp;

always @(posedge clk)

begin

if (reset)

temp <= 8'b0;

else

temp<={~shift_out,temp[7:1]};

end

assign shift_out=temp[0];

assign parallel_out=temp;

endmodule

TESTBENCH

module rtshift_tb();

reg clk,reset;

wire shift_out;

wire [7:0]parallel_out;

rtshift R1(clk,shift_out,reset,parallel_out);

initial

begin

 reset=1'b1;

 #100 reset=1'b0;

  #5000 $finish;

end

always

begin

  clk=1'b0;

  forever #50 clk=~clk;

  end

endmodule