Verilog code for the following using structured procedure and operators :excess 3 to decimal decoder.

module exs3dec(exs,dec);

input [3:0] exs;

output reg [3:0] dec;

always@(exs)

begin

dec=exs-4'b0011;

end

endmodule

TESTBENCH

module exs3dec_tb();

reg [3:0] EX3;

wire [3:0] DEC;

exs3dec E2D(EX3,DEC);

initial

begin

EX3=4'b0011;

   #50;    EX3=4'b0100;

    #50;    EX3=4'b0101;

    #50;    EX3=4'b0110;

    #50;    EX3=4'b0111;

    #50;    EX3=4'b1000;

    #50;    EX3=4'b1001;

    #50;    EX3=4'b1010;

    #50;    EX3=4'b1011;

    #50;    EX3=4'b1100;

    #50;    EX3=4'b1101;

    #50;    EX3=4'b1110;

    #50;    EX3=4'b1111;

    #150 $finish;

end

endmodule