YKH39Q8QKURV
Saturday, 12 January 2013
4 Floor Elevator Controller --- FPGA Implementation
on Xilinx FPGA and Xilinx ISE Design Suite
module elevator(x,ps,ns,up,down,clk,reset,close);
input [1:0]x;
input close,reset,clk;
output [1:0]ps,ns;
output up,down;
reg [1:0]ps,ns;
reg up,down;
always@(posedge clk)
begin
case({reset,close})
2'b00: ps<=0;
2'b01: ps<=0;
2'b10: ps<=ps;
2'b11: ps<=ns;
default: ps<=ps;
endcase
end
always@(close,reset,x)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
if(x==0) // if input is 0
ns=0; // presentstate is 0
else if(x==1) // defining state
ns=1;
else if(x==2)
ns=2;
else
ns=3;
end
else
begin
ns=0;
end
end
always @(x,ps,close,reset)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
case(x)
2'b00: begin
if(ps==1 || ps==2 || ps==3)
begin
up=0; // lift is going down
down=1;
end
else
begin
up=0; // no movement
down=0;
end
end
2'b01: begin
if(ps==2 || ps==3)
begin
up=0;
down=1;
end
else if(ps==0)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end
2'b10: begin
if(ps==0 || ps==1)
begin
up=1;
down=0;
end
else if(ps==3)
begin
up=0;
down=1;
end
else
begin
up=0;
down=0;
end
end
2'b11: begin
if(ps==0 || ps==2 || ps==1)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end
default: begin
up=0;
down=0;
end
endcase
end
else
begin
up=0;
down=0;
end
end
endmodule
TESTBENCH
`timescale 1ns / 1ps
module trial1_tb();
reg [1:0]x;
reg close,reset,clk;
wire [1:0]ps,ns;
wire up,down;
elevator ff(x,ps,ns,up,down,clk,reset,close);
initial
begin
clk=0; reset=0; x=2'b01; close=0;
#85; x=2'b10; close =1; reset=1;
#85; x=2'b00;
#85; x=2'b01;
#85; x=2'b11;
end
always
begin
#40; clk=(~clk);
end
endmodule
USER CONSTRAINTS FILE (ucf)
#clock source
NET "clk" LOC="C9";
NET "clk" PERIOD=80ns HIGH 50%;
#OUTPUT IO0
NET "ps<0>" LOC="F12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ps<1>" LOC="F11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<0>" LOC="E11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<1>" LOC="E12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "up" LOC="E9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "down" LOC="F9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
#INPUTS IO1
NET "x<0>" LOC="L13" | IOSTANDARD=LVTTL | PULLUP; #SW3;
NET "x<1>" LOC="L14" | IOSTANDARD=LVTTL | PULLUP; #SW2;
NET "close" LOC="N17" | IOSTANDARD=LVTTL | PULLUP; #SW0;
NET "reset" LOC="H18" | IOSTANDARD=LVTTL | PULLUP; #SW1
Write RTL verilog code that take an 8-bit number X and shifts it by 3 bits to the left to produce an 8-bit number Y, where the three least significant bits of Y are set to zeros. For example, if X = 8’b1010_1101, then Y = 8’b0110_1000.
module right_shift_by_3(X, Y);
input [7:0] X;
output [7:0] Y;
assign
Y={X[4:0],3'b000};
endmodule
TESTBENCH:
module right_shiftby3_tb();
reg [7:0]X;
wire [7:0]Y;
right_shift_by_3
RS3(X, Y);
initial
begin
X = 8'b10101101;
#100 X = 8'b10111101;
#100 X = 8'b10101100;
#100 X = 8'b11111111;
#100 X = 8'b10101000;
#100 X = 8'b10001101;
#100 X = 8'b10111100;
#250 $finish;
end
endmodule
Design a sequential circuit that has 1 data input (w) and 1 data output (z). The output z will become 1 if in the last 3 clock cycles the number of 1s on the input w has been greater than 1. Draw the FSM diagram and write/simulate the Verilog code to verify it.
module ques11(w,z,clock,reset);
input w,clock,reset;
output z;
reg z;
reg [3:0] prstate,nextstate;
parameter S0 = 4'b0000, S2 = 4'b0010, S3 = 4'b011, S4 =
4'b0100, S1 =4'b0001, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000;
always @ (posedge clock or negedge reset)
if (~reset)
prstate = S0;
else
prstate = nextstate;
always @ (prstate or w)
case (prstate)
S0: if (w) nextstate = S1;
else nextstate=S2;
S1: if (w) nextstate = S3;
else nextstate = S4;
S2: if (w) nextstate = S1;
else nextstate = S5;
S3: if (w) nextstate = S8;
else nextstate = S7;
S4: if (w) nextstate = S6;
else nextstate=S5;
S5: if (w) nextstate = S1;
else nextstate=S5;
S6: if (w) nextstate = S3;
else nextstate=S4;
S7: if (w) nextstate = S6;
else nextstate=S5;
S8: if (w) nextstate = S8;
else nextstate=S7;
default: nextstate
= S0;
endcase
always @ (prstate)
case (prstate)
S0: z = 0;
S1: z = 0;
S2: z = 0;
S3: z = 1;
S4: z = 0;
S5: z = 0;
S6: z = 1;
S7: z = 1;
S8: z = 1;
default: z= 1'bx;
endcase
endmodule
TESTBENCH:
module ques11_tb;
reg w,RST,CLK;
wire z;
ques11 M1(w,z,CLK,RST);
initial
begin
RST=1'b1;
#100 w=1'b0;
#100 w=1'b1;
#100 w=1'b1;
#100 w=1'b0;
#100 w=1'b0;
#100 w=1'b0;
#100 w=1'b1;
#100 w=1'b0;
#100 w=1'b1;
#100 w=1'b1;
#100 w=1'b1;
#100 w=1'b0;
#250 $finish;
end
always
begin
CLK=1'b1;
forever #50
CLK=~CLK;
end
endmodule
TWISTED RIGHT COUNTER
The RESET signal is a synchronous reset of the contents of the shift register to all 0’s. With reset inactive, on each positive edge on CLK, the twisted ring counter enters a new state. Due to the connection through the inverter, the twisted ring counter cycles through 2n different states on parallel_out where n is the number of bits in the shift register. Write a Verilog module description for the twisted ring counter shown using an always procedure to describe its activity.
module rtshift(clk,shift_out,reset,parallel_out);
input clk,reset;
output shift_out;
output [7:0]parallel_out;
reg [7:0]temp;
always @(posedge clk)
begin
if (reset)
temp <= 8'b0;
else
temp<={~shift_out,temp[7:1]};
end
assign shift_out=temp[0];
assign parallel_out=temp;
endmodule
TESTBENCH
module rtshift_tb();
reg clk,reset;
wire shift_out;
wire [7:0]parallel_out;
rtshift R1(clk,shift_out,reset,parallel_out);
initial
begin
reset=1'b1;
#100 reset=1'b0;
#5000 $finish;
end
always
begin
clk=1'b0;
forever #50
clk=~clk;
end
endmodule
Verilog task that uses a for loop to describe an iterative combinational circuit that compares two 8-bit operands A and B for equality E, and greater than G. Instantiate the task in a testbench and
simulate it for operands such that every bit of A and B take on value 1 and 0 sometime during the test and the outputs E and G take on all four possible combinations.
module compar(G,E,A,B);
input [7:0]A,B;
output reg E;
output reg G;
always@(A,B)
operation(G,E,A,B);
task operation;
output reg G;
output reg E;
input [7:0]A,B;
reg [7:0]x;
reg sum,prod;
integer i,j;
begin
for(i=0;i<8;i=i+1)
begin
x[i]=A[i]~^B[i];
end
E=&x;
sum=0;
for(i=0;i<8;i=i+1)
begin
j=i+1;
prod=A[i]&(~B[i]);
while(j<8)
begin
prod=x[j]∏
j=j+1;
end
sum=sum|prod;
end
G=sum;
end
endtask
endmodule
TESTBENCH
module compar_tb;
reg [7:0]A,B;
wire E,G;
compar C1(G,E,A,B);
initial
begin
A=00001111;
B=00000000;
#100 A=00000011;
B=00100000;
#100 A=00000011;
B=00000111;
#100 A=00000011;
B=0000010;
#100 A=11111111;
B=11111111;
#200 $finish;
end
endmodule
4-bit counter with the following count sequence (0, 1, 5, 3,7, 9, 11, 13, 15, 14, 12, 10, 2, 4)
module count(cout,clock,reset);
output [3:0]cout;
input clock,reset;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17;
wire na,nb,nc,nd;
dff D1(a,da,clock,reset);
dff D2(b,db,clock,reset);
dff D3(c,dc,clock,reset);
dff D4(d,dd,clock,reset);
not n1(na,a);
not n2(nb,b);
not n3(nc,c);
not n4(nd,d);
and a1(w1,nb,a);
and a2(w2,nd,a);
and a3(w3,nc,a);
and a4(w4,nb,nc);
or nexta(da,w1,w2,w3,w4);
and a5(w5,nb,d);
and a6(w6,nb,a,c);
and a7(w7,c,a,d);
and a8(w8,a,b,nc,nd);
and a9(w9,na,b,nc,d);
or nextb(db,w5,w6,w7,w8,w9);
and a10(w10,d,a,c);
and a11(w11,b,d,c);
and a12(w12,b,a,d);
and a13(w13,nc,a,nd);
and a14(w14,b,nc,nd);
or nextc(dc,w10,w11,w12,w13,w14);
and a15(w15,d,c);
and a16(w16,d,a);
and a17(w17,b,c);
or nextd(dd,w15,w16,w17);
buf b1(cout[0],a);
buf b2(cout[1],b);
buf b3(cout[2],c);
buf b4(cout[3],d);
endmodule
TESTBENCH
module count_tb;
wire [3:0]cout;
reg clk,rst;
count CC(cout,clk,rst);
initial
begin
rst=1'b1;
#100 rst=1'b0;
#1800 $finish;
end
always
begin
clk=1'b1;
forever #50
clk=~clk;
end
endmodule
module dff(q, d, clk, rst);
input d;
input clk, rst;
output reg q;
always @(posedge clk)
begin
if (rst) q <= 0;
else q <= d;
end
endmodule
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