**Write RTL verilog code that take an 8-bit number X and shifts it by 3 bits to**

**the left to produce an 8-bit number Y, where the three least significant bits of Y are set to**

**zeros. For example, if X = 8’b1010_1101, then Y = 8’b0110_1000.**

module right_shift_by_3(X, Y);

input [7:0] X;

output [7:0] Y;

assign
Y={X[4:0],3'b000};

endmodule

__TESTBENCH:__
module right_shiftby3_tb();

reg [7:0]X;

wire [7:0]Y;

right_shift_by_3
RS3(X, Y);

initial

begin

X = 8'b10101101;

#100 X = 8'b10111101;

#100 X = 8'b10101100;

#100 X = 8'b11111111;

#100 X = 8'b10101000;

#100 X = 8'b10001101;

#100 X = 8'b10111100;

#250 $finish;

end

endmodule

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