Saturday 12 January 2013

 YKH39Q8QKURV
4 Floor Elevator Controller --- FPGA Implementation
on Xilinx FPGA and Xilinx ISE Design Suite


`timescale 1ns / 1ps


module elevator(x,ps,ns,up,down,clk,reset,close);
input [1:0]x;
input close,reset,clk;
output [1:0]ps,ns;
output up,down;
reg [1:0]ps,ns;
reg up,down;

always@(posedge clk)
begin
case({reset,close})
2'b00: ps<=0;
2'b01: ps<=0;
2'b10: ps<=ps;
2'b11: ps<=ns;
default: ps<=ps;
endcase
end

always@(close,reset,x)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
if(x==0) // if input is 0
ns=0; // presentstate is 0
else if(x==1) // defining state
ns=1;
else if(x==2)
ns=2;
else
ns=3;
end
else
begin
ns=0;
end
end

always @(x,ps,close,reset)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
case(x)
2'b00: begin
if(ps==1 || ps==2 || ps==3)
begin
up=0; // lift is going down
down=1;
end
else
begin
up=0; // no movement
down=0;
end
end

2'b01: begin
if(ps==2 || ps==3)
begin
up=0;
down=1;
end
else if(ps==0)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end

2'b10: begin
if(ps==0 || ps==1)
begin
up=1;
down=0;
end
else if(ps==3)
begin
up=0;
down=1;
end
else
begin
up=0;
down=0;
end
end

2'b11: begin
if(ps==0 || ps==2 || ps==1)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end

default: begin
up=0;
down=0;
end
endcase
end
else
begin
up=0;
down=0;
end
end
endmodule



TESTBENCH

`timescale 1ns / 1ps

module trial1_tb();

reg [1:0]x;
reg close,reset,clk;
wire [1:0]ps,ns;
wire up,down;

elevator ff(x,ps,ns,up,down,clk,reset,close);

initial
begin
clk=0; reset=0; x=2'b01; close=0;

#85; x=2'b10; close =1; reset=1;
#85; x=2'b00;
#85; x=2'b01;
#85; x=2'b11;

end
always
begin
#40; clk=(~clk);

end

endmodule



USER CONSTRAINTS FILE (ucf)

#clock source
NET "clk" LOC="C9";
NET "clk" PERIOD=80ns HIGH 50%;
#OUTPUT IO0
NET "ps<0>" LOC="F12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ps<1>" LOC="F11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<0>" LOC="E11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<1>" LOC="E12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "up" LOC="E9"    | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "down" LOC="F9"  | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
#INPUTS IO1
NET "x<0>" LOC="L13"  | IOSTANDARD=LVTTL | PULLUP; #SW3;
NET "x<1>" LOC="L14"  | IOSTANDARD=LVTTL | PULLUP; #SW2;
NET "close" LOC="N17"  | IOSTANDARD=LVTTL | PULLUP; #SW0;
NET "reset" LOC="H18"   | IOSTANDARD=LVTTL | PULLUP; #SW1



Write RTL verilog code that take an 8-bit number X and shifts it by 3 bits to the left to produce an 8-bit number Y, where the three least significant bits of Y are set to zeros. For example, if X = 8’b1010_1101, then Y = 8’b0110_1000.


module right_shift_by_3(X, Y);
  input [7:0] X;
  output [7:0] Y;
 assign Y={X[4:0],3'b000};
endmodule

TESTBENCH: 
module right_shiftby3_tb();
  reg [7:0]X;
  wire [7:0]Y;
  right_shift_by_3 RS3(X, Y);
  initial
  begin
X = 8'b10101101;
#100 X = 8'b10111101;
#100 X = 8'b10101100;
#100 X = 8'b11111111;
#100 X = 8'b10101000;
#100 X = 8'b10001101;
#100 X = 8'b10111100;
#250 $finish;
end
endmodule


Design a sequential circuit that has 1 data input (w) and 1 data output (z). The output z will become 1 if in the last 3 clock cycles the number of 1s on the input w has been greater than 1. Draw the FSM diagram and write/simulate the Verilog code to verify it.


module ques11(w,z,clock,reset);
input w,clock,reset;
output z;
reg z;
reg [3:0] prstate,nextstate;
parameter S0 = 4'b0000, S2 = 4'b0010, S3 = 4'b011, S4 = 4'b0100, S1 =4'b0001, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000;
always @ (posedge clock or negedge reset)
if (~reset)
prstate = S0;
else
prstate = nextstate;
always @ (prstate or w)
case (prstate)
S0: if (w) nextstate = S1;
else nextstate=S2;
S1: if (w) nextstate = S3;
else nextstate = S4;
S2: if (w) nextstate = S1;
else nextstate = S5;
S3: if (w) nextstate = S8;
else nextstate = S7;
S4: if (w) nextstate = S6;
else nextstate=S5;
S5: if (w) nextstate = S1;
else nextstate=S5;
S6: if (w) nextstate = S3;
else nextstate=S4;
S7: if (w) nextstate = S6;
else nextstate=S5;
S8: if (w) nextstate = S8;
else nextstate=S7;
    default: nextstate = S0;
endcase
always @ (prstate)
case (prstate)
S0: z = 0;
S1: z = 0;
S2: z = 0;
S3: z = 1;
S4: z = 0;
S5: z = 0;
S6: z = 1;
S7: z = 1;
S8: z = 1;
default: z= 1'bx;
endcase
endmodule

TESTBENCH:
module ques11_tb;
reg w,RST,CLK;
wire z;
ques11 M1(w,z,CLK,RST);
initial
begin
  RST=1'b1;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b1;
  #100 w=1'b0;
  #100 w=1'b0;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b1;
  #100 w=1'b1;
 #100 w=1'b0;
  #250 $finish;
end
always
begin
  CLK=1'b1;
  forever #50 CLK=~CLK;
  end
endmodule

TWISTED RIGHT COUNTER

The RESET signal is a synchronous reset of the contents of the shift register to all 0’s. With reset inactive, on each positive edge on CLK, the twisted ring counter enters a new state. Due to the connection through the inverter, the twisted ring counter cycles through 2n different states on parallel_out where n is the number of bits in the shift register. Write a Verilog module description for the twisted ring counter shown using an always procedure to describe its activity.

module rtshift(clk,shift_out,reset,parallel_out);
input clk,reset;
output shift_out;
output [7:0]parallel_out;
reg [7:0]temp;
always @(posedge clk)
begin
if (reset)
temp <= 8'b0;
else
temp<={~shift_out,temp[7:1]};
end
assign shift_out=temp[0];
assign parallel_out=temp;
endmodule

TESTBENCH
module rtshift_tb();
reg clk,reset;
wire shift_out;
wire [7:0]parallel_out;
rtshift R1(clk,shift_out,reset,parallel_out);
initial
begin
 reset=1'b1;
 #100 reset=1'b0;
  #5000 $finish;
end
always
begin
  clk=1'b0;
  forever #50 clk=~clk;
  end
endmodule

Verilog task that uses a for loop to describe an iterative combinational circuit that compares two 8-bit operands A and B for equality E, and greater than G. Instantiate the task in a testbench and
simulate it for operands such that every bit of A and B take on value 1 and 0 sometime during the test and the outputs E and G take on all four possible combinations.


module compar(G,E,A,B);
  input [7:0]A,B;
  output reg E;
  output reg G;
  always@(A,B)
    operation(G,E,A,B);
task operation;
  output reg G;
  output reg E;
  input [7:0]A,B;
  reg [7:0]x;
  reg sum,prod;
  integer i,j;
  begin
    for(i=0;i<8;i=i+1)
    begin
    x[i]=A[i]~^B[i];
  end
  E=&x;
    sum=0;
    for(i=0;i<8;i=i+1)
    begin
    j=i+1;
    prod=A[i]&(~B[i]);
    while(j<8)
    begin
    prod=x[j]&prod;
    j=j+1;
  end
  sum=sum|prod;
end
   G=sum;
        end
endtask
endmodule

TESTBENCH
module compar_tb;
reg [7:0]A,B;
  wire E,G;
compar C1(G,E,A,B);
initial
begin
  A=00001111;
  B=00000000;
  #100 A=00000011;
  B=00100000;
   #100 A=00000011;
  B=00000111;
   #100 A=00000011;
  B=0000010;
   #100 A=11111111;
  B=11111111;
  #200 $finish;
end
endmodule


4-bit counter with the following count sequence (0, 1, 5, 3,7, 9, 11, 13, 15, 14, 12, 10, 2, 4)


module count(cout,clock,reset);
output [3:0]cout;
input clock,reset;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17;
wire na,nb,nc,nd;

dff D1(a,da,clock,reset);
dff D2(b,db,clock,reset);
dff D3(c,dc,clock,reset);
dff D4(d,dd,clock,reset);
not n1(na,a);
not n2(nb,b);
not n3(nc,c);
not n4(nd,d);

and a1(w1,nb,a);
and a2(w2,nd,a);
and a3(w3,nc,a);
and a4(w4,nb,nc);
or nexta(da,w1,w2,w3,w4);

and a5(w5,nb,d);
and a6(w6,nb,a,c);
and a7(w7,c,a,d);
and a8(w8,a,b,nc,nd);
and a9(w9,na,b,nc,d);
or nextb(db,w5,w6,w7,w8,w9);

and a10(w10,d,a,c);
and a11(w11,b,d,c);
and a12(w12,b,a,d);
and a13(w13,nc,a,nd);
and a14(w14,b,nc,nd);
or nextc(dc,w10,w11,w12,w13,w14);

and a15(w15,d,c);
and a16(w16,d,a);
and a17(w17,b,c);
or nextd(dd,w15,w16,w17);

buf b1(cout[0],a);
buf b2(cout[1],b);
buf b3(cout[2],c);
buf b4(cout[3],d);
endmodule

TESTBENCH
module count_tb;
wire [3:0]cout;
reg clk,rst;
count CC(cout,clk,rst);
initial
begin
   rst=1'b1;
   #100 rst=1'b0;
  #1800 $finish;
end
always
begin
  clk=1'b1;
  forever #50 clk=~clk;
  end
endmodule

D-flipflop

module dff(q, d, clk, rst);
input d;
input clk, rst;
output reg q;
always @(posedge clk)
begin
if (rst) q <= 0;
else q <= d;
end
endmodule


Verilog code to implement the function f(A,B,C,D) = Î£m(1,4,7,14,15)+ d(0,5,9) 

module func_manu(a,b,c,d,y);
  input a,b,c,d;
  output y;
  assign y=((~a&~c)|((b&c)&(a|b)));
endmodule
TESTBENCH
module func_tb();
  reg A,B,C,D;
  wire Y;
func_manu F1(A,B,C,D,Y);
  initial
  begin
    A=0;    B=0;    C=0;    D=0;
    #50;    A=0;    B=0;    C=0;    D=1;
    #50;    A=0;    B=0;    C=1;    D=0;
    #50;    A=0;    B=0;    C=1;    D=1;
    #50;    A=0;    B=1;    C=0;    D=0;
    #50;    A=0;    B=1;    C=0;    D=1;
    #50;    A=0;    B=1;    C=1;    D=0;
    #50;    A=0;    B=1;    C=1;    D=1;
    #50;    A=1;    B=0;    C=0;    D=0;
    #50;    A=1;    B=0;    C=0;    D=1;
    #50;    A=1;    B=0;    C=1;    D=0;
    #50;    A=1;    B=0;    C=1;    D=1;
    #50;    A=1;    B=1;    C=0;    D=0;
    #50;    A=1;    B=1;    C=0;    D=1;
    #50;    A=1;    B=1;    C=1;    D=0;
    #50;    A=1;    B=1;    C=1;    D=1;
    #250 $finish;
  end
endmodule

Verilog code for the following using structured procedure and operators :excess 3 to decimal decoder.

module exs3dec(exs,dec);
input [3:0] exs;
output reg [3:0] dec;
always@(exs)
begin
dec=exs-4'b0011;
end
endmodule

TESTBENCH
module exs3dec_tb();
reg [3:0] EX3;
wire [3:0] DEC;
exs3dec E2D(EX3,DEC);
initial
begin
EX3=4'b0011;
   #50;    EX3=4'b0100;
    #50;    EX3=4'b0101;
    #50;    EX3=4'b0110;
    #50;    EX3=4'b0111;
    #50;    EX3=4'b1000;
    #50;    EX3=4'b1001;
    #50;    EX3=4'b1010;
    #50;    EX3=4'b1011;
    #50;    EX3=4'b1100;
    #50;    EX3=4'b1101;
    #50;    EX3=4'b1110;
    #50;    EX3=4'b1111;
    #150 $finish;
end
endmodule

Multiplexer and De-multiplexer using nested if-else construct in Verilog

MULTIPLEXER 4-to-1
module mux_41(a,b,c,d,sel,y);
  input a,b,c,d;
  input [1:0]sel;
  output reg y;
always @(sel,a,b,c,d)
begin
if(sel[1]==0)
if(sel[0]==0)
y=a;
else
y=b;
else
if(sel[0]==0)
y=c;
else
y=d;
end
endmodule

TESTBENCH
module mux_41_tb();
  reg A,B,C,D;
  reg [1:0]SEL;
  wire Y;
mux_41 M1(A,B,C,D,SEL,Y);
  initial
  begin
    A=1;    B=0;    C=1;    D=0;
   SEL[0]=0;   SEL[1]=0;
    #150;    SEL[0]=1;
    #150;     SEL[1]=1;     SEL[0]=0;
    #150;     SEL[0]=1;
    #250 $finish;
  end
endmodule

DEMULTIPLEXER
module demux_14(d,sel,y);
  output reg [3:0] y;
  input [1:0] sel;
  input d;
always @(sel or d)
begin
  y=4'b0000;
if(sel[1]==0)
if(sel[0]==0)
y[0]=d; 
else
y[1]=d;
else
if(sel[0]==0)
y[2]=d;
else
y[3]=d;
end
endmodule

TESTBENCH
module demux_14_tb();
  wire [3:0] Y;
  reg [1:0] SEL;
  reg D;
demux_14 DM(D,SEL,Y);
  initial
  begin
    D=1'b1;
   SEL=2'b10;
    #50;    SEL[0]=1;
    #50;     SEL[1]=0;     SEL[0]=0;
    #50;     SEL[0]=1;
    #250 $finish;
  end

Code Convertor & parity generators using reduction operators in Verilog

BINARY TO GRAY CONVERTER
module bin2gray(b,g);
  input [3:0] b;
  output [3:0] g;
  assign g[3]=b[3];
  assign g[2]=^b[3:2];
  assign g[1]=^b[2:1];
  assign g[0]=^b[1:0];
endmodule

TESTBENCH:
module bin2gray_tb();
  wire [3:0] G;
  reg [3:0] B;
  bin2gray BG1(B,G);
  initial
  begin
    B=4'b0000;
   #50;    B=4'b0001;
    #50;    B=4'b0010;
    #50;    B=4'b0011;
    #50;    B=4'b0100;
    #50;    B=4'b0101;
    #50;    B=4'b0110;
    #50;    B=4'b0111;
    #50;    B=4'b1000;
    #50;    B=4'b1001;
    #50;    B=4'b1010;
    #50;    B=4'b1011;
    #50;    B=4'b1100;
    #50;    B=4'b1101;
    #50;    B=4'b1110;
    #50;    B=4'b1111;
    #250 $finish;
  end
endmodule

PARITY GENERATOR
module parity(a,p);
  input [3:0]a;
  output p;
  assign p=^a;
endmodule

TESTBENCH:
module parity_tb();
  reg [3:0] A;
  wire P;
parity P1(A,P);
  initial
  begin
    A=4'b0000;
    #50;    A=4'b0001;
    #50;    A=4'b0010;
    #50;    A=4'b0011;
    #50;    A=4'b0100;
    #50;    A=4'b0101;
    #50;    A=4'b0110;
    #50;    A=4'b0111;
    #50;    A=4'b1000;
    #50;    A=4'b1001;
    #50;    A=4'b1010;
    #50;    A=4'b1011;
    #50;    A=4'b1100;
    #50;    A=4'b1101;
    #50;    A=4'b1110;
    #50;    A=4'b1111;
    #250 $finish;
  end
endmodule



Decoder and Encoder using case statements in Verilog
module decod_bm(ain, y);
input [2:0] ain;
output reg [7:0] y;
always@(ain)
begin
case(ain)
3'b000:y=8'b00000001;
3'b001:y=8'b00000010;
3'b010:y=8'b00000100;
3'b011:y=8'b00001000;
3'b100:y=8'b00010000;
3'b101:y=8'b00100000;
3'b110:y=8'b01000000;
3'b111:y=8'b10000000;
default:y=4'bxxxx;
endcase
end
endmodule

TESTBENCH:
module decod_tb();
  reg [2:0]IN;
  wire [7:0] OUT;
decod_bm DCR(IN, OUT);
  initial
  begin
    IN=3'b000;
    #50;    IN=3'b001;
    #50;    IN=3'b010;
    #50;     IN=3'b011;
    #50;     IN=3'b100;
     #50;     IN=3'b101;
    #50;     IN=3'b110;
    #250 $finish;
  End
endmodule

ENCODER
module encod_83(aout,yin);                                                       
input [7:0] yin;
output reg [2:0] aout;
always@(yin)
begin
case(yin)
8'b00000001:aout=3'b000;
8'b00000010:aout=3'b001;
8'b00000100:aout=3'b010;
8'b00001000:aout=3'b011;
8'b00010000:aout=3'b100;
8'b00100000:aout=3'b101;
8'b01000000:aout=3'b110;
8'b10000000:aout=3'b111;
default:aout=2'bxx;
endcase
end
endmodule

TESTBENCH:
module encod_tb();
  reg [7:0] IN;
  wire [2:0] OUT;
encod_83 ENCR(OUT,IN);
  initial
  begin
    IN=8'b00000001;
    #50;    IN=8'b00000010;
    #50;    IN=8'b00000100;
    #50;     IN=8'b00001000;
      #50;     IN=8'b00010000;
      #50;     IN=8'b00100000;
      #50;     IN=8'b01000000;
    #250 $finish;                                                                          
  end
endmodule

Half-Subtractor and Full-Subtractor using dataflow modeling in Verilog
HALF SUBTRACTOR
module halfsub_df(a,b,diff,borr);
input a,b;
output diff,borr;
assign diff=a^b;
assign borr=~a&b;
endmodule

TESTBENCH:
module halfsub_tb();
  reg A,B;
  wire DIFF,BORR;
halfsub_df HA1(A,B,DIFF,BORR);
  initial
  begin
    A=0;    B=0;
    #50;    B=1;
    #50;     B=0;      A=1;
    #50;     B=1;
    #250 $finish;
  end
endmodule
FULL SUBTRACTOR
module fullsub_df(a,b,c,diff,borr);
input a,b,c;
output diff,borr;
assign diff=(a^b^c);
assign borr=((~a&b)|(~a&c)|(b&c));
endmodule

TESTBENCH:
module fullsub_tb();
  reg A,B,C;
  wire DIFF,BORR;
fullsub_df FS(A,B,C,DIFF,BORR);
  initial
  begin
    A=0;    B=0;    C=0;
    #50;    C=1;
    #50;    B=1;    C=0;
    #50;      C=1;
     #50;     A=1;     B=0;     C=0;
     #50;     C=1;
     #50;     C=0;     B=1;
     #50;     C=1;
    #250 $finish;
  end
endmodule


Half-Adder and Full-Adder using structural Modeling in Verilog
HALF ADDER:
module ha_sm(a,b,sum,carry);
input a,b;
output sum,carry;
xor g1(sum,a,b);
and g2(carry,a,b);
endmodule

TESTBENCH:
module halfadd_sm_tb();
  reg A,B;
  wire SUM,CARRY;
ha_sm HA1(A,B,SUM,CARRY);
  initial
  begin
    A=0;    B=0;
    #50;    B=1;
    #50;     A=1;      B=0;
    #50;     B=1;
    #250 $finish;
  end
endmodule

FULL ADDER
module fa_sm(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
xor g1(w1,a,b);
and g2(w3,a,b);
xor g3(sum,c,w1);
and g4(w2,w1,c);
or g5(carry,w3,w2);
endmodule

TESTBENCH
module fulladd_sm_tb();
  reg A,B,C;
  wire SUM,CARRY;
fa_sm F1(A,B,C,SUM,CARRY);
  initial
  begin
    A=0;    B=0;    C=0;
    #50;    C=1;
    #50;     B=1;      C=0;
    #50;     C=1;
     #50;     A=1;     B=0;     C=0;
     #50;     C=1;
     #50;     C=0;     B=1;
     #50;     C=1;
    #250 $finish;
  end
endmodule

Basic Gates Using Dataflow, Structural, Behavioral Modeling using Verilog
STRUCTURAL
module gates_sm(a,b,A1,O1,XO1,NA1,NO1,XNO1,N1);
input a,b;
output A1,O1,XO1,NA1,NO1,XNO1,N1;
and(A1,a,b);
or(O1,a,b);
xor(XO1,a,b);
nand(NA1,a,b);
nor(NO1,a,b);
xnor(XNO1,a,b);
not(N1,a);
endmodule


DATAFLOW
module gates_dm(a,b,A2,O2,XO2,NA2,NO2,XNO2,N2);
input a,b;
output A2,O2,XO2,NA2,NO2,XNO2,N2;
assign A2=a&b;
assign O2=a|b;
assign XO2=a^b;
assign NA2=~(a&b);
assign NO2=~(a|b);
assign XNO2=~(a^b);
assign N2=~a;
endmodule


BEHAVIOURAL
module gates_bm(a,b,A3,O3,XO3,NA3,NO3,XNO3,N3);
input a,b;
output reg A3,O3,XO3,NA3,NO3,XNO3,N3;
always@(a,b)
begin
A3=a&b;
O3=a|b;
XO3=a^b;
NA3=~(a&b);
NO3=~(a|b);
XNO3=~(a^b);
N3=~a;
end
endmodule

TESTBENCH:
module gates_sm_tb();
  reg A,B;
  wire a1,o1,xo1,na1,no1,xno1,n1;
 gates_sm g1(A,B,a1,o1,xo1,na1,no1,xno1,n1);
  initial
  begin
    A=0;   B=0;
    #50;    B=1;
    #50;     A=1;      B=0;
    #50;     B=1;
    #250 $finish;
  end
endmodule