Saturday 12 January 2013



Half-Adder and Full-Adder using structural Modeling in Verilog
HALF ADDER:
module ha_sm(a,b,sum,carry);
input a,b;
output sum,carry;
xor g1(sum,a,b);
and g2(carry,a,b);
endmodule

TESTBENCH:
module halfadd_sm_tb();
  reg A,B;
  wire SUM,CARRY;
ha_sm HA1(A,B,SUM,CARRY);
  initial
  begin
    A=0;    B=0;
    #50;    B=1;
    #50;     A=1;      B=0;
    #50;     B=1;
    #250 $finish;
  end
endmodule

FULL ADDER
module fa_sm(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
xor g1(w1,a,b);
and g2(w3,a,b);
xor g3(sum,c,w1);
and g4(w2,w1,c);
or g5(carry,w3,w2);
endmodule

TESTBENCH
module fulladd_sm_tb();
  reg A,B,C;
  wire SUM,CARRY;
fa_sm F1(A,B,C,SUM,CARRY);
  initial
  begin
    A=0;    B=0;    C=0;
    #50;    C=1;
    #50;     B=1;      C=0;
    #50;     C=1;
     #50;     A=1;     B=0;     C=0;
     #50;     C=1;
     #50;     C=0;     B=1;
     #50;     C=1;
    #250 $finish;
  end
endmodule

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