4 Floor Elevator Controller --- FPGA Implementation

on Xilinx FPGA and Xilinx ISE Design Suite

`timescale 1ns / 1ps


module elevator(x,ps,ns,up,down,clk,reset,close);
input [1:0]x;
input close,reset,clk;
output [1:0]ps,ns;
output up,down;
reg [1:0]ps,ns;
reg up,down;

always@(posedge clk)
begin
case({reset,close})
2'b00: ps<=0;
2'b01: ps<=0;
2'b10: ps<=ps;
2'b11: ps<=ns;
default: ps<=ps;
endcase
end

always@(close,reset,x)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
if(x==0) // if input is 0
ns=0; // presentstate is 0
else if(x==1) // defining state
ns=1;
else if(x==2)
ns=2;
else
ns=3;
end
else
begin
ns=0;
end
end

always @(x,ps,close,reset)
begin
if(close==1 && reset==1) //if close and reset are 1
begin
case(x)
2'b00: begin
if(ps==1 || ps==2 || ps==3)
begin
up=0; // lift is going down
down=1;
end
else
begin
up=0; // no movement
down=0;
end
end

2'b01: begin
if(ps==2 || ps==3)
begin
up=0;
down=1;
end
else if(ps==0)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end

2'b10: begin
if(ps==0 || ps==1)
begin
up=1;
down=0;
end
else if(ps==3)
begin
up=0;
down=1;
end
else
begin
up=0;
down=0;
end
end

2'b11: begin
if(ps==0 || ps==2 || ps==1)
begin
up=1;
down=0;
end
else
begin
up=0;
down=0;
end
end

default: begin
up=0;
down=0;
end
endcase
end
else
begin
up=0;
down=0;
end
end
endmodule



TESTBENCH

`timescale 1ns / 1ps

module trial1_tb();

reg [1:0]x;
reg close,reset,clk;
wire [1:0]ps,ns;
wire up,down;

elevator ff(x,ps,ns,up,down,clk,reset,close);

initial
begin
clk=0; reset=0; x=2'b01; close=0;

#85; x=2'b10; close =1; reset=1;
#85; x=2'b00;
#85; x=2'b01;
#85; x=2'b11;

end
always
begin
#40; clk=(~clk);

end

endmodule



USER CONSTRAINTS FILE (ucf)

#clock source
NET "clk" LOC="C9";
NET "clk" PERIOD=80ns HIGH 50%;
#OUTPUT IO0
NET "ps<0>" LOC="F12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ps<1>" LOC="F11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<0>" LOC="E11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "ns<1>" LOC="E12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "up" LOC="E9"    | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
NET "down" LOC="F9"  | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
#INPUTS IO1
NET "x<0>" LOC="L13"  | IOSTANDARD=LVTTL | PULLUP; #SW3;
NET "x<1>" LOC="L14"  | IOSTANDARD=LVTTL | PULLUP; #SW2;
NET "close" LOC="N17"  | IOSTANDARD=LVTTL | PULLUP; #SW0;
NET "reset" LOC="H18"   | IOSTANDARD=LVTTL | PULLUP; #SW1