Saturday 12 January 2013


Design a sequential circuit that has 1 data input (w) and 1 data output (z). The output z will become 1 if in the last 3 clock cycles the number of 1s on the input w has been greater than 1. Draw the FSM diagram and write/simulate the Verilog code to verify it.


module ques11(w,z,clock,reset);
input w,clock,reset;
output z;
reg z;
reg [3:0] prstate,nextstate;
parameter S0 = 4'b0000, S2 = 4'b0010, S3 = 4'b011, S4 = 4'b0100, S1 =4'b0001, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000;
always @ (posedge clock or negedge reset)
if (~reset)
prstate = S0;
else
prstate = nextstate;
always @ (prstate or w)
case (prstate)
S0: if (w) nextstate = S1;
else nextstate=S2;
S1: if (w) nextstate = S3;
else nextstate = S4;
S2: if (w) nextstate = S1;
else nextstate = S5;
S3: if (w) nextstate = S8;
else nextstate = S7;
S4: if (w) nextstate = S6;
else nextstate=S5;
S5: if (w) nextstate = S1;
else nextstate=S5;
S6: if (w) nextstate = S3;
else nextstate=S4;
S7: if (w) nextstate = S6;
else nextstate=S5;
S8: if (w) nextstate = S8;
else nextstate=S7;
    default: nextstate = S0;
endcase
always @ (prstate)
case (prstate)
S0: z = 0;
S1: z = 0;
S2: z = 0;
S3: z = 1;
S4: z = 0;
S5: z = 0;
S6: z = 1;
S7: z = 1;
S8: z = 1;
default: z= 1'bx;
endcase
endmodule

TESTBENCH:
module ques11_tb;
reg w,RST,CLK;
wire z;
ques11 M1(w,z,CLK,RST);
initial
begin
  RST=1'b1;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b1;
  #100 w=1'b0;
  #100 w=1'b0;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b0;
  #100 w=1'b1;
  #100 w=1'b1;
  #100 w=1'b1;
 #100 w=1'b0;
  #250 $finish;
end
always
begin
  CLK=1'b1;
  forever #50 CLK=~CLK;
  end
endmodule

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