Basic Gates Using Dataflow, Structural, Behavioral Modeling using Verilog

STRUCTURAL

module gates_sm(a,b,A1,O1,XO1,NA1,NO1,XNO1,N1);

input a,b;

output A1,O1,XO1,NA1,NO1,XNO1,N1;

and(A1,a,b);

or(O1,a,b);

xor(XO1,a,b);

nand(NA1,a,b);

nor(NO1,a,b);

xnor(XNO1,a,b);

not(N1,a);

endmodule

DATAFLOW

module gates_dm(a,b,A2,O2,XO2,NA2,NO2,XNO2,N2);

input a,b;

output A2,O2,XO2,NA2,NO2,XNO2,N2;

assign A2=a&b;

assign O2=a|b;

assign XO2=a^b;

assign NA2=~(a&b);

assign NO2=~(a|b);

assign XNO2=~(a^b);

assign N2=~a;

endmodule

BEHAVIOURAL

module gates_bm(a,b,A3,O3,XO3,NA3,NO3,XNO3,N3);

input a,b;

output reg A3,O3,XO3,NA3,NO3,XNO3,N3;

always@(a,b)

begin

A3=a&b;

O3=a|b;

XO3=a^b;

NA3=~(a&b);

NO3=~(a|b);

XNO3=~(a^b);

N3=~a;

end

endmodule

TESTBENCH:

module gates_sm_tb();

  reg A,B;

  wire a1,o1,xo1,na1,no1,xno1,n1;

 gates_sm g1(A,B,a1,o1,xo1,na1,no1,xno1,n1);

  initial

  begin

    A=0;   B=0;

    #50;    B=1;

    #50;     A=1;      B=0;

    #50;     B=1;

    #250 $finish;

  end

endmodule